<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Mar 09 22:14:18 2015</TD>
  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2014.4 (64-bit)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>1071353</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>210881784_0_0_155</TD>
  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a100t</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>csg324</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>2df465911d91556191d44d1b504edcc7</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>ba3909a8d0d94a8f84b70ed1b1489d11</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>0</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i5-3337U CPU @ 1.80GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>1796 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>4.000 GB</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>srcsetcount=2</TD>
   <TD>constraintsetcount=1</TD>
   <TD>designmode=RTL</TD>
   <TD>prproject=false</TD>
</TR><TR ALIGN='LEFT'>   <TD>reconfigpartitioncount=0</TD>
   <TD>reconfigmodulecount=0</TD>
   <TD>hdproject=false</TD>
   <TD>partitioncount=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>currentsynthesisrun=synth_1</TD>
   <TD>currentimplrun=impl_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>totalsynthesisruns=1</TD>
   <TD>totalimplruns=1</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=1</TD>
    <TD>carry4=8</TD>
    <TD>fdre=36</TD>
    <TD>gnd=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=4</TD>
    <TD>lut1=32</TD>
    <TD>lut2=1</TD>
    <TD>lut3=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=1</TD>
    <TD>lut5=1</TD>
    <TD>lut6=10</TD>
    <TD>obuf=25</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuft=38</TD>
    <TD>vcc=2</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=1</TD>
    <TD>carry4=8</TD>
    <TD>fdre=36</TD>
    <TD>gnd=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=4</TD>
    <TD>lut1=32</TD>
    <TD>lut2=1</TD>
    <TD>lut3=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=1</TD>
    <TD>lut5=1</TD>
    <TD>lut6=10</TD>
    <TD>obuf=25</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuft=38</TD>
    <TD>vcc=2</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>placer</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>lut=20</TD>
    <TD>ff=36</TD>
    <TD>bram36=0</TD>
    <TD>bram18=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ctrls=3</TD>
    <TD>dsp=0</TD>
    <TD>iob=29</TD>
    <TD>bufg=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>global_clocks=1</TD>
    <TD>pll=0</TD>
    <TD>bufr=0</TD>
    <TD>nets=140</TD>
</TR><TR ALIGN='LEFT'>    <TD>movable_instances=98</TD>
    <TD>pins=501</TD>
    <TD>bogomips=0</TD>
    <TD>effort=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>threads=2</TD>
    <TD>placer_timing_driven=1</TD>
    <TD>timing_constraints_exist=1</TD>
    <TD>placer_runtime=1.922000</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-verbose=default::[not_specified]</TD>
    <TD>-hier=default::power</TD>
    <TD>-no_propagation=default::[not_specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-file=[specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-xpe=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-vid=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-l=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
    <TD>flow_state=routed</TD>
    <TD>family=artix7</TD>
</TR><TR ALIGN='LEFT'>    <TD>die=xc7a100tcsg324-1</TD>
    <TD>package=csg324</TD>
    <TD>speedgrade=-1</TD>
    <TD>version=2014.4</TD>
</TR><TR ALIGN='LEFT'>    <TD>platform=nt64</TD>
    <TD>temp_grade=commercial</TD>
    <TD>process=typical</TD>
    <TD>simulation_file=None</TD>
</TR><TR ALIGN='LEFT'>    <TD>netlist_net_matched=NA</TD>
    <TD>pct_clock_constrained=1.000000</TD>
    <TD>pct_inputs_defined=25</TD>
    <TD>user_junc_temp=25.5 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>ambient_temp=25.0 (C)</TD>
    <TD>user_effective_thetaja=4.6</TD>
    <TD>airflow=250 (LFM)</TD>
    <TD>heatsink=medium (Medium Profile)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_thetasa=4.6 (C/W)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>board_layers=12to15 (12 to 15 Layers)</TD>
    <TD>user_thetajb=5.7 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_board_temp=25.0 (C)</TD>
    <TD>junction_temp=25.5 (C)</TD>
    <TD>input_toggle=12.500000</TD>
    <TD>output_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>bi-dir_toggle=12.500000</TD>
    <TD>output_enable=1.000000</TD>
    <TD>bidir_output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>ff_toggle=12.500000</TD>
    <TD>ram_enable=50.000000</TD>
    <TD>ram_write=50.000000</TD>
    <TD>dsp_output_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>set/reset_probability=0.000000</TD>
    <TD>enable_probability=0.990000</TD>
    <TD>toggle_rate=False</TD>
    <TD>signal_rate=False</TD>
</TR><TR ALIGN='LEFT'>    <TD>static_prob=False</TD>
    <TD>read_saif=False</TD>
    <TD>on-chip_power=0.106458</TD>
    <TD>dynamic=0.009365</TD>
</TR><TR ALIGN='LEFT'>    <TD>effective_thetaja=4.6</TD>
    <TD>thetasa=4.6 (C/W)</TD>
    <TD>thetajb=5.7 (C/W)</TD>
    <TD>off-chip_power=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>clocks=0.000603</TD>
    <TD>logic=0.000034</TD>
    <TD>signals=0.000092</TD>
    <TD>i/o=0.008636</TD>
</TR><TR ALIGN='LEFT'>    <TD>devstatic=0.097092</TD>
    <TD>vccint_voltage=1.000000</TD>
    <TD>vccint_total_current=0.015799</TD>
    <TD>vccint_dynamic_current=0.000806</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_static_current=0.014994</TD>
    <TD>vccaux_voltage=1.800000</TD>
    <TD>vccaux_total_current=0.018455</TD>
    <TD>vccaux_dynamic_current=0.000314</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_static_current=0.018141</TD>
    <TD>vcco33_voltage=3.300000</TD>
    <TD>vcco33_total_current=0.006423</TD>
    <TD>vcco33_dynamic_current=0.002423</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_static_current=0.004000</TD>
    <TD>vcco25_voltage=2.500000</TD>
    <TD>vcco25_total_current=0.000000</TD>
    <TD>vcco25_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_static_current=0.000000</TD>
    <TD>vcco18_voltage=1.800000</TD>
    <TD>vcco18_total_current=0.000000</TD>
    <TD>vcco18_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_static_current=0.000000</TD>
    <TD>vcco15_voltage=1.500000</TD>
    <TD>vcco15_total_current=0.000000</TD>
    <TD>vcco15_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_static_current=0.000000</TD>
    <TD>vcco135_voltage=1.350000</TD>
    <TD>vcco135_total_current=0.000000</TD>
    <TD>vcco135_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_static_current=0.000000</TD>
    <TD>vcco12_voltage=1.200000</TD>
    <TD>vcco12_total_current=0.000000</TD>
    <TD>vcco12_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_static_current=0.000000</TD>
    <TD>vccaux_io_voltage=1.800000</TD>
    <TD>vccaux_io_total_current=0.000000</TD>
    <TD>vccaux_io_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_static_current=0.000000</TD>
    <TD>vccbram_voltage=1.000000</TD>
    <TD>vccbram_total_current=0.000245</TD>
    <TD>vccbram_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_static_current=0.000245</TD>
    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavcc_total_current=0.000000</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_static_current=0.000000</TD>
    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>mgtavtt_total_current=0.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_static_current=0.000000</TD>
    <TD>vccadc_voltage=1.800000</TD>
    <TD>vccadc_total_current=0.020000</TD>
    <TD>vccadc_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_static_current=0.020000</TD>
    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_clock_activity=Medium</TD>
    <TD>confidence_level_io_activity=Medium</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_internal_activity=Medium</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_overall=Medium</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>slice_luts_used=20</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_available=63400</TD>
    <TD>slice_luts_util_percentage=0.03</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=20</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_available=63400</TD>
    <TD>lut_as_logic_util_percentage=0.03</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_available=19000</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=36</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_available=126800</TD>
    <TD>slice_registers_util_percentage=0.02</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_used=36</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_available=126800</TD>
    <TD>register_as_flip_flop_util_percentage=0.02</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_available=126800</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>f7_muxes_used=0</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_available=31700</TD>
    <TD>f7_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_available=15850</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_used=14</TD>
    <TD>slice_fixed=0</TD>
    <TD>slice_available=15850</TD>
    <TD>slice_util_percentage=0.08</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_used=6</TD>
    <TD>slicel_fixed=0</TD>
    <TD>slicem_used=8</TD>
    <TD>slicem_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=20</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_available=63400</TD>
    <TD>lut_as_logic_util_percentage=0.03</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_output_only_used=0</TD>
    <TD>using_o5_output_only_fixed=</TD>
    <TD>using_o6_output_only_used=19</TD>
    <TD>using_o6_output_only_fixed=</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_used=1</TD>
    <TD>using_o5_and_o6_fixed=</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=19000</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
    <TD>lut_as_distributed_ram_used=0</TD>
    <TD>lut_as_distributed_ram_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_shift_register_used=0</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_flip_flop_pairs_used=51</TD>
    <TD>lut_flip_flop_pairs_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_flip_flop_pairs_available=63400</TD>
    <TD>lut_flip_flop_pairs_util_percentage=0.08</TD>
    <TD>fully_used_lut_ff_pairs_used=5</TD>
    <TD>fully_used_lut_ff_pairs_fixed=</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_ff_pairs_with_unused_lut_used=31</TD>
    <TD>lut_ff_pairs_with_unused_lut_fixed=</TD>
    <TD>lut_ff_pairs_with_unused_flip_flop_used=15</TD>
    <TD>lut_ff_pairs_with_unused_flip_flop_fixed=</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_used=3</TD>
    <TD>minimum_number_of_registers_lost_to_control_set_restriction_used=12(Lost)</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_used=0</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_available=135</TD>
    <TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo*_used=0</TD>
    <TD>ramb36_fifo*_fixed=0</TD>
    <TD>ramb36_fifo*_available=135</TD>
    <TD>ramb36_fifo*_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_used=0</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_available=270</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_used=0</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_available=240</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_used=1</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_util_percentage=3.12</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_used=0</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_available=24</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_available=6</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_available=6</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_available=12</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_used=0</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_available=96</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_used=0</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_available=24</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_used=0</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_available=4</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_used=0</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_available=1</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_used=0</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_available=1</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_used=0</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_available=2</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_fixed=0</TD>
    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_used=0</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_available=1</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_used=0</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_available=1</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>fdre_used=36</TD>
    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>obuf_used=25</TD>
    <TD>obuf_functional_category=IO</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_used=10</TD>
    <TD>lut6_functional_category=LUT</TD>
    <TD>carry4_used=8</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3_used=7</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>ibuf_used=4</TD>
    <TD>ibuf_functional_category=IO</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5_used=1</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut4_used=1</TD>
    <TD>lut4_functional_category=LUT</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_used=1</TD>
    <TD>lut2_functional_category=LUT</TD>
    <TD>lut1_used=1</TD>
    <TD>lut1_functional_category=LUT</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufg_used=1</TD>
    <TD>bufg_functional_category=Clock</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>diff_sstl15_r=0</TD>
    <TD>hstl_ii=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>lvttl=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl15=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos33=1</TD>
    <TD>sstl135_r=0</TD>
    <TD>lvcmos15=0</TD>
    <TD>lvcmos18=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>mobile_ddr=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>pci33_3=0</TD>
    <TD>lvcmos12=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hsul_12=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii_18=0</TD>
    <TD>sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl18_ii=0</TD>
    <TD>sstl15=0</TD>
    <TD>sstl135=0</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_i=0</TD>
    <TD>rsds_25=0</TD>
    <TD>diff_hstl_ii=0</TD>
    <TD>tmds_33=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_i_18=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>diff_hstl_ii_18=0</TD>
    <TD>ppds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_i=0</TD>
    <TD>diff_sstl18_ii=0</TD>
    <TD>diff_sstl135=0</TD>
    <TD>diff_sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>router</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>lut=21</TD>
    <TD>ff=36</TD>
    <TD>bram36=0</TD>
    <TD>bram18=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ctrls=3</TD>
    <TD>dsp=0</TD>
    <TD>iob=29</TD>
    <TD>bufg=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>global_clocks=1</TD>
    <TD>pll=0</TD>
    <TD>bufr=0</TD>
    <TD>nets=140</TD>
</TR><TR ALIGN='LEFT'>    <TD>movable_instances=98</TD>
    <TD>pins=501</TD>
    <TD>bogomips=0</TD>
    <TD>high_fanout_nets=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>effort=2</TD>
    <TD>threads=2</TD>
    <TD>router_timing_driven=1</TD>
    <TD>timing_constraints_exist=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>congestion_level=0</TD>
    <TD>estimated_expansions=80682</TD>
    <TD>actual_expansions=139324</TD>
    <TD>router_runtime=48.549000</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-part=xc7a100tcsg324-1</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-top=n4fpga</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-generic=default::[not_specified]</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
    <TD>-constrset=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
</TR><TR ALIGN='LEFT'>    <TD>-flatten_hierarchy=default::rebuilt</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-directive=default::default</TD>
    <TD>-rtl=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-bufg=default::12</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-shreg_min_size=default::3</TD>
    <TD>-mode=default::default</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-resource_sharing=default::auto</TD>
    <TD>-control_set_opt_threshold=default::auto</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:36s</TD>
    <TD>memory_peak=576.230MB</TD>
    <TD>memory_gain=391.086MB</TD>
    <TD>hls_ip=0</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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